Partcl
Design a chip in minutes
Designs chips in minutes using GPU-accelerated, physics-informed software—dramatically cutting R&D cycles and costs.
- Founders
- William Salcedo, Vamshi Balanaga
- YC batch
- P25
Company posts
Summaries from the company’s own website.
- Partcl/HRT Macro Placement Challenge — $20K Grand Prize ↗
Partcl says it is launching an open competition with Hudson River Trading to develop macro placement algorithms for ASIC physical design. The post outlines the challenge goals, prize structure, deadline, and validation criteria on benchmark designs.